The present invention relates to a phase change memory device and a method for manufacturing the same, and more particularly, to a phase change memory device having improved current drivability brought about by an increased area of a diode and a method for manufacturing the same.
Memory devices are generally divided into volatile RAMs (random access memory) which lose inputted information when power is interrupted and nonvolatile ROMs (read only memory) which can maintain the stored state of inputted information even when power is interrupted. As to volatile RAMs, a DRAM (dynamic RAM) and an SRAM (static RAM) can be mentioned. As to nonvolatile ROMs, a flash memory device such as an EEPROM (electrically erasable and programmable ROM) can be mentioned.
While DRAM are excellent memory devices, DRAMs require high charge storing capacity. To this end, since the surface area of DRAM electrodes must be relatively large, then it is difficult to accomplish a high level of integration. Further, since flash memory devices have two gates are stacked on each other, then a high operation voltage is required as compared to other comparable devices. According, flash memory devices require a separate booster circuit to generate the requisite voltage needed for the write and delete operations. Therefore, flash memory devices also make it is difficult to accomplish a high level of integration.
Under these circumstances, it is understandable that research has continued to actively develop a novel alternate memory devices which still have simple configurations and still are capable of accomplishing a high level of integration while retaining many of the desirable characteristics of the non-volatile memory devices. As an example, a phase change memory device has recently been disclosed in the art.
Phase change memory devices function by having a phase change occurs in a phase change layer interposed between a bottom electrode and a top electrode. This phase change layer transitions between an ordered crystalline state to an unordered amorphous crystalline state. This phase change transition can be driven by an electric current flowing between the bottom electrode and the top electrode. Information can be stored in these types of cells by exploiting the physical difference in the resistances between the crystalline and amorphous states. Specifically, in the phase change memory device the specific resistance of the phase change layer in the amorphous state is higher than the specific resistance of the phase change layer in the crystalline state. Accordingly, a phase change memory device can be developed that senses the current flowing through the phase change layer in a read state to determine whether information stored in a phase change memory cell has a logic value corresponding to ‘1’ or ‘0’.
In order to manufacture a phase change memory device of 512 Mb or greater, a method of adopting vertical PN diodes as switching elements has been proposed. In the case of adopting the vertical PN diodes, advantages are provided in that a cell size can be decreased below 6 femtometers2. Also, since the PN diodes have great dependency on the sectional area thereof, the current drivability of the phase change memory device changes in proportion to the area of the PN diodes.
However, as the area of the diodes decreases in conformity with the trend toward the high integration of semiconductor devices, the current drivability of the phase change memory device deteriorates in the conventional art, whereby the characteristics and the reliability of the devices in the conventional art degrade.
Hence, in order to increase the area of diodes, a method has been proposed, in which the CD (critical dimension) of contact holes for diodes is increased overall. Nevertheless, in this case, since the CD of the upper surfaces of the diodes formed in the contact holes increases, a bridge phenomenon is likely to occur between adjoining diodes.